1. Field of the Invention
The present invention relates to a method of manufacturing semiconductor devices, and more specifically, to a wafer alignment method.
2. Discussion of Related Art
Recently, semiconductor devices used for embedded memory in the field of system ICs or SOC (System On Chip) have memory devices, such as DRAM, SRAM, flash memory and EEPROM, and logic elements for field applications formed on a semiconductor substrate. There is a need for manufacturing technology of semiconductor devices, wherein different elements are formed in two or more semiconductor substrates and the substrates are then stacked.
FIGS. 1a to 1c are cross-sectional views for explaining a conventional wafer alignment method.
Referring to FIG. 1a, an interlayer insulating film 12 is formed on a semiconductor substrate 10 having a memory device formed in. While a final metal line is formed on the interlayer insulating film 12, bonding pads 14 of the memory device, which are to be bonded to a semiconductor substrate 20 having a logic element formed in, are formed. A first protection film 16 is formed on the bonding pads 14 and is then selectively etched to expose predetermined portions of the bonding pads 14 of the memory device.
Referring to FIG. 1b, an interlayer insulating film 22 is formed on the semiconductor substrate 20 having the logic element formed in. While a final metal line is formed on the interlayer insulating film 22, bonding pads 24 of a logic element, which are to be bonded to the semiconductor substrate 10 having the memory device formed in, are formed. A second protection film 26 is formed on the bonding pads 24, and is then selectively etched to open the bonding pads 24 of the logic element.
Referring to FIG. 1c, in order to connect the semiconductor substrate 10 of the memory device and the semiconductor substrate 20 of the logic element, the semiconductor substrate 10 of the memory device and the semiconductor substrate 20 of the logic element are stacked so that the bonding pads 14 formed in the semiconductor substrate of the memory device and the bonding pads 24 formed in the semiconductor substrate of the logic element are in contact with each other in a state where a bottom surface of the semiconductor substrate 20 of the logic element is oriented upwardly.
Thereafter, the semiconductor substrate 10 of the memory device and the semiconductor substrate 20 of the logic element, which are stacked together, are annealed to electrically connect the bonding pads 14 formed in the semiconductor substrate of the memory device and the bonding pads 24 formed in the semiconductor substrate of the logic element.
If the semiconductor substrates respectively provided in the memory device and the logic element are stacked, however, a misalignment phenomenon frequently occurs. This makes difficult electrical connection of the semiconductor substrate in which the memory device is provided and the semiconductor substrate in which the logic element is provided.